1. Field of the Invention
The present invention relates to a system decoder of an optical disk reproducing apparatus, and in particular, to a system decoder having error correcting memories for high-speed data transmission and a method for controlling the same.
2. Description of the Related Art
An optical disk reproducing apparatus such as a laser disk (LD) player or a compact disk (CD) player has been widely accepted for home use since an optical disk technique which can read data recorded in a recording medium by using a laser beam was established about 20 years ago. A recording/reproducing apparatus using such an optical disk has been put to practical use. Recently, with the development of shortwave laser or recording/reproducing technique in addition to an overwrite technique, progress has been made in increasing the recording density of the optical disk.
Meanwhile, a digital image compression technique has been advancing rapidly. In particular, the MPEG2 (Moving Picture Experts Group 2) can reproduce picture quality to a sufficient degree so as to be received in the household at a data transmission rate of close to 10 Mbps. In the field of audio reproduction, an audio compression technique AC-3 which is capable of reproducing multichannel audio leads to high tone quality and multi-sound. Together with a recordable digital video (or versatile) disk, a digital video disk (DVD) is expected to play an important role in a CD-ROM as well as a video tape recorder (VTR) which is an existing video recording/reproducing apparatus. Such a DVD is one type of digital moving picture disk media and is a multimedia storage device of high picture quality and high tone quality which can store an MPEG2 digital image of 2 hours or more.
FIG. 1 schematically illustrates a general DVD reproducing apparatus. As an optical disk 10 rotates by a disk motor 16, an optical pickup 13 which is driven by a sled pickup motor 14 and includes a head 12 converts data reproduced from the optical disk 10 into an analog RF (Radio Frequency) signal. This analog RF signal is shaped into a pulse waveform and a data stream ESM is transmitted to a digital PLL (Phase Locked Loop) 20 and a system decoder 18. The system decoder 18 demodulates, error-corrects, and descrambles the data stream ESM. The digital PLL 20 including a phase comparator, a voltage controlled oscillator, a frequency divider, etc., generates a first clock in synchronism with a signal reproduced from the optical disk 10. A disk driving controller 22 controls a constant linear velocity of the rotation of the optical disk 10 and other disk related operations in consideration of frequency servo, phase servo, etc., according to a frame synchronizing signal Sf provided from a synchronous detector (not shown) of the system decoder 18.
A microprocessor 24 controls the overall operation of the DVD reproducing apparatus according to a control program. For instance, if a data transmission start signal is received from an audio decoder 42, a video decoder 36 or a ROM (Read Only Memory) decoder 32, the microprocessor 24 generates a transmission control signal. A system clock generator 26, which is a crystal oscillator, generates a second clock of a system clock PLCK and transmits the system clock PLCK to the disk driving controller 22 and an error corrector (not shown). A first memory 28 connected to the system decoder 18 is a memory for correcting an error and uses a SRAM (Static Random Access Memory). A second memory 30 which is a track buffer memory uses a DRAM (Dynamic Random Access Memory). The ROM decoder 32 which is mainly contained in a host (for example, a personal computer) operates according to a command of the host and transmits data generated from the system decoder 18 to the host according to an interface type. A demultiplexer 34 receives audio and video signals from the system decoder 34, and transmits multiplexed audio and video signals to the AC3/MPEG audio decoder 42 and the MPEG2 video decoder 36, respectively. Video data and audio data respectively decoded from the video decoder 36 and the audio decoder 42 are transmitted to an NTSC (or PAL) encoder 38 and a digital-to-analog (D/A) converter 44 and output through a monitor 40 and a speaker 46, respectively.
FIG. 2 is a detailed block diagram of the system decoder 18 shown in FIG. 1. The first memory 28 used for error correction is the SRAM. The second memory 30 used for data buffering is the DRAM. The data stream ESM read through the head 12 is demodulated through a 32-bit shift register 102 and a 16-8 demodulator 104 of an EFM demodulator 100. A synchronous detector 106 detects the frame synchronous signal Sf from data generated from the 32-bit shift register 102 and transmits the detected frame synchronous signal Sf to the digital PLL 20. Meanwhile, data demodulated through the EFM demodulator 100 is stored in the first memory 28 under the control of an error correcting code (ECC) memory controller 108. The data stored in the first memory 28 is read by blocks under the control of the ECC memory controller 108 and then transmitted to an error corrector 110. Data error-corrected from the error corrector 110 is transmitted to a descrambler and error detector 112 under the control of the ECC memory controller 108. A descrambler of the descrambler and error detector 112 restores data scrambled in the process of encoding data, and an error detector thereof detects an error of the descrambled data. The descrambling and error detection are carried out by sectors. Error information detected from the descrambler and error detector 112 is stored in the second memory 30 under the control of a microprocessor memory access controller 116, together with data. The microprocessor memory access controller 116 controls a buffer write controller 114, a buffer read controller 118 and a track buffer memory controller 120 under the control of the microprocessor 24 through a microprocessor interface 122. The buffer write controller 114 writes data descrambled and error-detected from the descrambler and error detector 112 in the second memory 30 under the control of the microprocessor memory access controller 116. The buffer read controller 118 reads the data stored in the second memory 30 under the control of the microprocessor memory access controller 116 and transmits the read data to an audio/video (A/V) decoder interface and a DVD-ROM interface 126. The microprocessor interface 122 interfaces transmitting/receiving signals between the system decoder 18 and the microprocessor 24.
In operation, the synchronous detection, identification (ID) detection and demodulation of the data stream are performed. Next, the error detection and correction are implemented. Thereafter, the descrambling, error detection and track buffering of the error-corrected data are executed. The first memory 28 has a first region for buffering EFM demodulated data, a second region for error-correcting a buffered error correcting block horizontally and vertically, and a third region for transmitting error-corrected data to the second memory 30. That is, the ECC memory controller 108 stores the EFM demodulated data in the first region of the first memory 28, reads and error-corrects the data stored in the first region by blocks using the second region, stores the error-corrected data in the third region of the first memory 28, and transmits the data stored in the third region to the second memory 30. In this data processing, the ECC memory controller 108 processes data in the order of: data reading, error correction, data transmission, data reading, error correction and data transmission. That is, since data is accessed from three regions of one memory, an error correcting speed is deteriorated. Therefore, the optical disk reproducing apparatus having such a system decoder 18 has a slow data processing speed and a slow data transmission speed.